The present invention relates to a semiconductor device. For example, the present invention relates to a semiconductor device capable of executing a plurality of programs in parallel through pipeline processing.
In recent years, in semiconductor devices, a number of multi-thread processors capable of executing a plurality of programs in a single processor have been proposed. The multi-thread processor like this includes a plurality of threads each of which generates an independent instruction flow. Meanwhile, there is a technique called “virtualization” that makes one hardware device look as if it is a plurality of hardware devices. This virtualization technique is realized by interposing a management software program called “VMM (Virtual Machine Monitor)” or “hypervisor” between the OS (Operating System) and the hardware (processor or IO). FIG. 20 shows a hierarchical structure of a system to which the virtualization technique is applied. As shown in FIG. 20, the system to which the virtualization technique is applied has such a configuration that a hypervisor program is interposed between the hardware and the OS. When a plurality of virtual machines that are logically defined are operated in a multi-thread processor, a thread is assigned to one of the plurality of virtual machines. Further, in the multi-thread processor, the parallel executions of virtual machines are realized by executing the virtual machines on hardware threads. FIG. 21 shows corresponding relation between virtual machines and threads. In the example shown in FIG. 21, two threads are assigned to each of virtual machines VM0 to Vm2.
Further, a privilege level is defined for a program(s) to be executed in the processor according to the importance of the resource to be accessed. Further, the quality of software is determined by a plurality of factors including development management, programming, and verification. Further, among the programs to be executed on the processor, a program(s) requiring a high reliability level is developed under strict management so that its operation can be grasped in detail. That is, the reliability level of a program is determined based on what kind of development process the program has been developed through. Further, for example, control is performed so that access to a resource that requires a high privilege level is permitted to a program having a high reliability level, but it is not permitted to a program having a low reliability level.
However, even in the processor like this, it is necessary to perform a process for a resource that requires a high privilege level for its access in response to a request from a user application or a guest OS for which a low privilege level is defined. In such a case, the processor starts a hypervisor program in response to a request from a user application or a guest OS and performs the required process through the hypervisor program. As a result, when access to a resource requiring a high privilege level for its access is requested from a user application or a guest OS, the process takes time for switching the program, and thereby causing a problem that the processing performance of the processor deteriorates.
Therefore, Japanese Unexamined Patent Application Publication No. 2005-56017 discloses a technique for reducing the time required for switching the program. In Japanese Unexamined Patent Application Publication No. 2005-56017, the processor has a privilege register for a guest OS. Then, when access to a resource requiring high reliability occurs, the process is completed without starting the hypervisor program as long as the request can be satisfied by the process for the guest OS alone. In this way, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2005-56017 can reduce the frequency at which the hypervisor program is started.